?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 1 the sst logo, superflash, and flashflex are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications features: ? 8-bit 8051-compatible microcontroller (mcu) with embedded superflash memory ? fully software compatible ? development toolset compatible ? pin-for-pin package compatible sst89e5xrc operation ? 0 to 40 mhz at 5v sst89v5xrc operation ? 0 to 33 mhz at 3v total 512 byte internal ram (256 byte by default + 256 byte enabled by software) single block superflash eeprom ? sst89e/v54rc: 16 kbyte primary partition + 1 kbyte secondary partition ? sst89e/v52rc: 8 kbyte primary partition + 1 kbyte secondary partition ? sst89e/v51rc: 4 kbyte primary partition + 1 kbyte secondary partition ? primary partition is divided into four pages ? secondary partition has one page ? individual page security lock ? in-system programming (isp) ? in-application programming (iap) ? small-sector architecture: 128-byte sector size support external address range up to 64 kbyte of program and data memory three high-current port 1 pins (16 ma each) three 16-bit timers/counters full-duplex, enhanced uart ? framing error detection ? automatic address recognition eight interrupt sources at 4 priority levels programmable watchdog timer (wdt) programmable counter array (pca) four 8-bit i/o ports (32 i/o pins) second dptr register low emi mode (inhibit ale) spi serial interface standard 12 clocks per cycle, the device has an option to double the speed to 6 clocks per cycle. ttl- and cmos-compatible logic levels low power modes ? power-down mode with external interrupt wake-up ? idle mode selectable operation clock ? divide down to 1/4, 1/16, 1/256, or 1/1024th temperature ranges: ? commercial (0c to +70c) ? industrial (-40c to +85c) packages available ? 44-lead plcc ? 44-lead tqfp all non-pb (lead-free) devices are rohs compliant product description the sst89e/v54rc, sst89e/v52rc, and sst89e/ v51rc are members of the flashflex51 family of 8-bit microcontroller products designed and manufactured with sst?s patented and proprietary superflash cmos semi- conductor process technology. the split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for our customers.the devices use the 8051 instruction set and are pin-for-pin compatible with stan- dard 8051 microcontroller devices. the device comes with 17/9/5 kbyte of on-chip flash eeprom program memory which is divided into 2 inde- pendent program memory partitions. the primary partition occupies 16/8/4 kbyte of internal program memory space and the secondary partition occupies 1 kbyte of internal program memory space. the flash memory can be programmed via a standard 87c5x otp eprom programmer fitted with a special adapter and firmware for sst?s devices. during power-on reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-system programming (isp) opera- tion. the devices are designed to be programmed in-sys- tem on the printed circuit board for maximum flexibility. the device is pre-programmed with an example of the boot- strap loader in memory, demonstrating the initial user pro- gram code loading or subse quent user code updating via an isp operation. a sample bootstrap loader is available for the user?s reference and convenience only; sst does not guarantee its functionality or usefulness. chip-erase opera- tions will erase the pre-programmed sample code. in addition to 17/9/5 kbyt e of superflash eeprom pro- gram memory on-chip, the device can address up to 64 kbyte of external program memory. in addition to 512 x8 bits of on-chip ram, up to 64 kbyte of external ram can be addressed. flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc sst89e/ve5xrc flashflex51 mcu
2 preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 sst?s highly reliable, patented superflash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash eeproms. these advantages translate into significant cost and reliability benefits for our customers. 1.0 functional blocks 8 interrup ts superflash eeprom primary partition 4k/8k/16k x8 1 secondary partition 1k x8 i/o i/o i/o i/o watchdog timer interrupt control 8051 cpu core ram 512 x8 security lock i/o port 0 i/o port 1 i/o port 2 i/o port 3 8-bit enhanced uart spi timer 0 (16-bit) timer 1 (16-bit) timer 2 (16-bit) 8 8 8 8 1259 b1.1 pca flash control unit 8 oscillator 1. 16k x8 for sst89e/v54rc 8k x8 for sst89e/v52rc 4k x8 for sst89e/v51rc alu, acc, b-register, instruction register, program counter, timing and control f unctional b lock d iagram
preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc 3 ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 2.0 pin assignments figure 2-1: p in a ssignments for 44- lead tqfp figure 2-2: p in a ssignments for 44- lead plcc ( cex2 / mosi) p1.5 ( cex3 / miso) p1.6 (cex4 / sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# nc ale/prog # psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 (ss# / cex 1) p1.3 (cex0) p1.2 (eci) p1.1 (t2 ex) p1.0 (t2) nc v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) ( wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 1259 44-tqfp tqj p2 .0 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 44-lead tqfp top view 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 ( cex2 / mosi) p1.5 ( cex3 / miso) p1.6 (cex4 / sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# nc ale/prog # psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 p1.4 (ss# / cex1 ) p1.3 (cex0) p1.2 (eci) p1.1 (t2 ex) p1.0 (t2) nc v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) ( wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 44-lead plcc top view 1259 44-plcc nj p3.0
4 preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 2.1 pin descriptions table 2-1: p in d escriptions (1 of 2) symbol type 1 name and functions p0[7:0] i/o port 0: port 0 is an 8-bit open drain bi-directional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins that have ?1?s written to them float, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. in this application, it uses strong internal pull-ups when transitioning to ?1?s. port 0 also receives the code bytes during the external host mode programming, and outpu ts the code bytes during the external host mode verification. external pull-ups are required during program verification or as a general purpose i/o port. p1[7:0] i/o with internal pull-up port 1: port 1 is an 8-bit bi-directional i/o port with internal pull-ups. the port 1 output buffers can drive ls ttl inputs. port 1 pins are pulled high by the internal pull-ups when ?1?s are writ- ten to them and can be used as i nputs in this state. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. p1[5, 6, 7] have high current drive of 16 ma. port 1 also receives the low-order address byte during the external host mode programming and verification. p1[0] i/o t2: external count input to timer/counte r 2 or clock-out from timer/counter 2 p1[1] i t2ex: timer/counter 2 capture/reload trigger and direction control p1[2] i eci: external clock input this signal is the external clock input for the pca. p1[3] i/o cex0: capture/compare external i/o for pca module 0 each capture/compare module connects to a port 1 pin for external i/o. when not used by the pca, this pin can handle standard i/o. p1[4] i/o ss#: slave port select input for spi or cex1: capture/compare external i/o for pca module 1 p1[5] i/o mosi: master output line, slave input line for spi or cex2: capture/compare external i/o for pca module 2 p1[6] i/o miso: master input line, slave output line for spi or cex3: capture/compare external i/o for pca module 3 p1[7] i/o sck: master clock output, slave clock input line for spi or cex4: capture/compare external i/o for pca module 4 p2[7:0] i/o with internal pull-up port 2: port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 2 pins that are externa lly pulled low will source current because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external pro- gram memory and during accesses to external data memory that use 16-bit address (movx@dptr). in this application, it uses strong internal pull-ups when transitioning to ?1?s. port 2 also receives the high-order address byte during the external host mode programming and verification. p3[7:0] i/o with internal pull-up port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. the port 3 output buffers can drive ls ttl inputs. port 3 pins are pulled high by the internal pull-ups when ?1?s are writ- ten to them and can be used as i nputs in this state. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also receives the high- order address byte during the external host mode programming and verification. p3[0] i rxd: universal asynchronous receiver/t ransmitter (uart) - receive input p3[1] o txd: uart - transmit output p3[2] i int0#: external interrupt 0 input
preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc 5 ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 p3[3] i int1#: external interrupt 1 input p3[4] i t0: external count input to timer/counter 0 p3[5] i t1: external count input to timer/counter 1 p3[6] o wr#: external data memory write strobe p3[7] o rd#: external data memory read strobe psen# i/o program store enable: psen# is the read strobe to external program. when the device is executing from internal program memory, psen# is inactive (high). when the device is exe- cuting code from external program memory, psen# is activated twice each machine cycle, except that two psen# activations are skipped during each access to external data memory. a forced high-to-low input tran sition on the psen# pin while the rst input is continually held high for more than 10 machine cycles will cause the device to enter external host mode pro- gramming. rst i reset: while the oscillator is runnin g, a ?high? logic state on this pin for two machine cycles will reset the device. if the psen# pin is driven by a high-to-low input transition while the rst input pin is held ?high,? the device will enter the external host mode, otherwise the device will enter the normal operation mode. ea# i external access enable: ea# must be connected to v ss in order to enable the device to fetch code from the external program memory. ea# must be strapped to v dd for internal pro- gram execution. however, disable-extern-boot will disable ea#, and program execution is only possible from internal program memory. the ea# pin can tolerate a high voltage 2 of 12v. ale/prog# i/o address latch enable: ale is the output signal for latching the low byte of the address dur- ing an access to external memory. this pin is also the programming pulse input (prog#) for flash programming. normally the ale 3 is emitted at a constant rate of 1/6 the crystal fre- quency 4 and can be used for external timing and clocking. one ale pulse is skipped during each access to external data memory. however, if ao is set to 1, ale is disabled. nc i/o no connect xtal1 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 o crystal 2: output from the inverting oscillator amplifier. v dd i power supply v ss i ground t2-1.0 1259 1. i = input; o = output 2. it is not necessary to receive a 12v pr ogramming supply voltage during flash programming. 3.ale loading issue: when ale pin experienc es higher loading (>30pf) during the reset, the mcu may accidentally enter into mode s other than normal working mode. the solution is to add a pull-up resistor of 3-50 k ? to v dd , e.g. for ale pin. 4. for 6 clock mode, ale is emitted at 1/3 of crystal frequency. table 2-1: p in d escriptions (c ontinued ) (2 of 2) symbol type 1 name and functions
6 preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 3.0 product ordering information device speed suffix1 suffix2 sst89 x 5xrc -xx -x -xx x x environmental attribute e 1 = non-pb package modifier i = 40 pins j = 44 leads package type n = plcc tq = tqfp operation temperature c = commercial = 0c to +70c i = industrial = -40c to +85c operating frequency 33 = 0-33mhz 40 = 0-40mhz feature set rc = single block, dual partitions (blank) = single block, single partitions flash memory size 4 = 16 kbyte 2 = 8 kbyte 1 = 4 kbyte voltage rang e e = 4.5-5.5v v = 2.7-3.6v product series 89 = c51 core 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc 7 ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 3.1 valid combinations note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. valid combinations for sst89e51rc sst89e51rc-40-c-nj sst89e51rc-40-c-tqj sst89e51rc-40-c-nje sst89e51rC-40-C-TQJE sst89e51rc-40-i-nj sst89e51rc-40-i-tqj sst89e51rc-40-i-nje sst89e51rc-40-i-tqje valid combinations for sst89v51rc sst89v51rc-33-c-nj sst89v51rc-33-c-tqj sst89v51rc-33-c-nje sst89v51rc-33-c-tqje sst89v51rc-33-i-nj sst89v51rc-33-i-tqj sst89v51rc-33-i-nje sst89v51rc-33-i-tqje valid combinations for sst89e52rc sst89e52rc-40-c-nj sst89e52rc-40-c-tqj sst89e52rc-40-c-nje sst89e52rC-40-C-TQJE sst89e52rc-40-i-nj sst89e52rc-40-i-tqj sst89e52rc-40-i-nje sst89e52rc-40-i-tqje valid combinations for sst89v52rc sst89v52rc-33-c-nj sst89v52rc-33-c-tqj sst89v52rc-33-c-nje sst89v52rc-33-c-tqje sst89v52rc-33-i-nj sst89v52rc-33-i-tqj sst89v52rc-33-i-nje sst89v52rc-33-i-tqje valid combinations for sst89e54rc sst89e54rc-40-c-nj sst89e54rc-40-c-tqj sst89e54rc-40-c-nje sst89e54rC-40-C-TQJE sst89e54rc-40-i-nj sst89e54rc-40-i-tqj sst89e54rc-40-i-nje sst89e54rc-40-i-tqje valid combinations for sst89v54rc sst89v54rc-33-c-nj sst89v54rc-33-c-tqj sst89v54rc-33-c-nje sst89v54rc-33-c-tqje sst89v54rc-33-i-nj sst89v54rc-33-i-tqj sst89v54rc-33-i-nje sst89v54rc-33-i-tqje
8 preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 4.0 packaging diagrams 44- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nj .025 .045 .013 .021 .590 .630 .100 .112 .020 min. .165 .180 top view side view bottom view 144 .026 .032 .500 ref. 44-plcc-nj -7 note: 1. complies with jedec publication 95 ms-018 ac dimensions (except as noted), although some dimensions may be more strin gent. ? = jedec min is .650; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc. .050 bsc. .026 .032 .042 .056 .646 ? .656 .042 .048 .042 .048 optional p in #1 identifier .646 ? .656 .685 .695 .685 .695 .020 r. max. .147 .158 r. x45?
preliminary specifications flashflex51 mcu sst89e51rc / sst89e52rc / sst89e54rc sst89v51rc / sst89v52rc / sst89v54rc 9 ?2005 silicon storage technology, inc. s71259(01)-00-000 2/05 44- lead t hin q uad f lat p ack (tqfp) sst p ackage c ode : tqj n ote: 1. complies with jedec publication 95 ms-026 acb dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (0.05) mm. 4. package body dimensions do not include mold flash. maximum allowable mold flash is .25mm. 44-tqfp-tqj-7 .45 .75 10.00 0.10 12.00 0.25 1.00 ref 0?- 7? 1 11 33 23 12 22 44 34 1.2 max. .95 1.05 .05 .15 pin #1 identifier .30 .45 .09 .20 .80 bsc 12.00 0.25 10.00 0.10 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com
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